73 lines
2.9 KiB
Plaintext
73 lines
2.9 KiB
Plaintext
|
Marvell Orion SPI device
|
||
|
|
|
||
|
|
Required properties:
|
||
|
|
- compatible : should be on of the following:
|
||
|
|
- "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
|
||
|
|
- "marvell,armada-370-spi", for the Armada 370 SoCs
|
||
|
|
- "marvell,armada-375-spi", for the Armada 375 SoCs
|
||
|
|
- "marvell,armada-380-spi", for the Armada 38x SoCs
|
||
|
|
- "marvell,armada-390-spi", for the Armada 39x SoCs
|
||
|
|
- "marvell,armada-xp-spi", for the Armada XP SoCs
|
||
|
|
- reg : offset and length of the register set for the device.
|
||
|
|
This property can optionally have additional entries to configure
|
||
|
|
the SPI direct access mode that some of the Marvell SoCs support
|
||
|
|
additionally to the normal indirect access (PIO) mode. The values
|
||
|
|
for the MBus "target" and "attribute" are defined in the Marvell
|
||
|
|
SoC "Functional Specifications" Manual in the chapter "Marvell
|
||
|
|
Core Processor Address Decoding".
|
||
|
|
The eight register sets following the control registers refer to
|
||
|
|
chip-select lines 0 through 7 respectively.
|
||
|
|
- cell-index : Which of multiple SPI controllers is this.
|
||
|
|
Optional properties:
|
||
|
|
- interrupts : Is currently not used.
|
||
|
|
|
||
|
|
Example:
|
||
|
|
spi@10600 {
|
||
|
|
compatible = "marvell,orion-spi";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
cell-index = <0>;
|
||
|
|
reg = <0x10600 0x28>;
|
||
|
|
interrupts = <23>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
Example with SPI direct mode support (optionally):
|
||
|
|
spi0: spi@10600 {
|
||
|
|
compatible = "marvell,orion-spi";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
cell-index = <0>;
|
||
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
|
||
|
|
<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
|
||
|
|
<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
|
||
|
|
<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
|
||
|
|
<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
|
||
|
|
<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
|
||
|
|
<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
|
||
|
|
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
|
||
|
|
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
|
||
|
|
interrupts = <23>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
To enable the direct mode, the board specific 'ranges' property in the
|
||
|
|
'soc' node needs to add the entries for the desired SPI controllers
|
||
|
|
and its chip-selects that are used in the direct mode instead of PIO
|
||
|
|
mode. Here an example for this (SPI controller 0, device 1 and SPI
|
||
|
|
controller 1, device 2 are used in direct mode. All other SPI device
|
||
|
|
are used in the default indirect (PIO) mode):
|
||
|
|
soc {
|
||
|
|
/*
|
||
|
|
* Enable the SPI direct access by configuring an entry
|
||
|
|
* here in the board-specific ranges property
|
||
|
|
*/
|
||
|
|
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
|
||
|
|
<MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
|
||
|
|
<MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
|
||
|
|
<MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */
|
||
|
|
|
||
|
|
For further information on the MBus bindings, please see the MBus
|
||
|
|
DT documentation:
|
||
|
|
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
|