73 lines
2.9 KiB
Plaintext
73 lines
2.9 KiB
Plaintext
Marvell Orion SPI device
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Required properties:
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- compatible : should be on of the following:
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- "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
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- "marvell,armada-370-spi", for the Armada 370 SoCs
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- "marvell,armada-375-spi", for the Armada 375 SoCs
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- "marvell,armada-380-spi", for the Armada 38x SoCs
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- "marvell,armada-390-spi", for the Armada 39x SoCs
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- "marvell,armada-xp-spi", for the Armada XP SoCs
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- reg : offset and length of the register set for the device.
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This property can optionally have additional entries to configure
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the SPI direct access mode that some of the Marvell SoCs support
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additionally to the normal indirect access (PIO) mode. The values
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for the MBus "target" and "attribute" are defined in the Marvell
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SoC "Functional Specifications" Manual in the chapter "Marvell
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Core Processor Address Decoding".
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The eight register sets following the control registers refer to
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chip-select lines 0 through 7 respectively.
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- cell-index : Which of multiple SPI controllers is this.
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Optional properties:
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- interrupts : Is currently not used.
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Example:
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spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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reg = <0x10600 0x28>;
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interrupts = <23>;
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status = "disabled";
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};
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Example with SPI direct mode support (optionally):
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spi0: spi@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
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<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
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<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
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<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
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<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
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<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
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<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
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<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
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<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
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interrupts = <23>;
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status = "disabled";
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};
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To enable the direct mode, the board specific 'ranges' property in the
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'soc' node needs to add the entries for the desired SPI controllers
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and its chip-selects that are used in the direct mode instead of PIO
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mode. Here an example for this (SPI controller 0, device 1 and SPI
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controller 1, device 2 are used in direct mode. All other SPI device
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are used in the default indirect (PIO) mode):
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soc {
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/*
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* Enable the SPI direct access by configuring an entry
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* here in the board-specific ranges property
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*/
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>, /* internal regs */
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<MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>, /* BootROM */
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<MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
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<MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>; /* SPI1-DEV2 */
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For further information on the MBus bindings, please see the MBus
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DT documentation:
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Documentation/devicetree/bindings/bus/mvebu-mbus.txt
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