336 lines
10 KiB
C
336 lines
10 KiB
C
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/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software and related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an express
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* license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#ifndef _ARM_SMMU_REGS_H
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#define _ARM_SMMU_REGS_H
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/* SMMU global address space */
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#define ARM_SMMU_GR0(smmu) ((smmu)->base)
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#define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
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#define ARM_SMMU_PME(smmu) ((smmu)->base + (3 << (smmu)->pgshift))
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/*
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* SMMU global address space with conditional offset to access secure
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* aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
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* nsGFSYNR0: 0x450)
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*/
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#define ARM_SMMU_GR0_NS(smmu) \
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((smmu)->base + \
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((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
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? 0x400 : 0))
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/* Page table bits */
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#define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
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#define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
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#define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
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#define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
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#define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
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#define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
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#define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
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#if PAGE_SIZE == SZ_4K
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#define ARM_SMMU_PTE_CONT_ENTRIES 16
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#elif PAGE_SIZE == SZ_64K
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#define ARM_SMMU_PTE_CONT_ENTRIES 32
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#else
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#define ARM_SMMU_PTE_CONT_ENTRIES 1
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#endif
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#define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
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#define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
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/* Stage-1 PTE */
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#define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
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#define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
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#define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
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#define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
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/* Stage-2 PTE */
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#define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
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#define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
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#define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
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#define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
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#define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
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#define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
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/* Configuration registers */
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#define ARM_SMMU_GR0_sCR0 0x0
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#define ARM_SMMU_GR0_sCR2 0x8
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#define ARM_SMMU_GR0_sACR 0x10
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#define sCR0_CLIENTPD (1 << 0)
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#define sCR0_GFRE (1 << 1)
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#define sCR0_GFIE (1 << 2)
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#define sCR0_GCFGFRE (1 << 4)
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#define sCR0_GCFGFIE (1 << 5)
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#define sCR0_USFCFG (1 << 10)
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#define sCR0_VMIDPNE (1 << 11)
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#define sCR0_PTM (1 << 12)
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#define sCR0_FB (1 << 13)
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#define sCR0_BSU_SHIFT 14
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#define sCR0_BSU_MASK 0x3
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/* Identification registers */
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#define ARM_SMMU_GR0_ID0 0x20
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#define ARM_SMMU_GR0_ID1 0x24
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#define ARM_SMMU_GR0_ID2 0x28
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#define ARM_SMMU_GR0_ID3 0x2c
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#define ARM_SMMU_GR0_ID4 0x30
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#define ARM_SMMU_GR0_ID5 0x34
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#define ARM_SMMU_GR0_ID6 0x38
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#define ARM_SMMU_GR0_ID7 0x3c
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#define ARM_SMMU_GR0_sGFAR 0x40
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#define ARM_SMMU_GR0_sGFSR 0x48
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#define ARM_SMMU_GR0_sGFSYNR0 0x50
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#define ARM_SMMU_GR0_sGFSYNR1 0x54
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#define ARM_SMMU_GR0_sGFSYNR2 0x58
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#define ARM_SMMU_GR0_nsCR0 0x400
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#define ARM_SMMU_GR0_nsGFAR 0x440
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#define ARM_SMMU_GR0_nsGFSR 0x448
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#define ARM_SMMU_GR0_nsGFSYNR0 0x450
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#define ARM_SMMU_GR0_nsGFSYNR1 0x454
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#define ARM_SMMU_GR0_nsGFSYNR2 0x458
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#define ARM_SMMU_GR0_PIDR0 0xfe0
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#define ARM_SMMU_GR0_PIDR1 0xfe4
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#define ARM_SMMU_GR0_PIDR2 0xfe8
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#define ID0_S1TS (1 << 30)
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#define ID0_S2TS (1 << 29)
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#define ID0_NTS (1 << 28)
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#define ID0_SMS (1 << 27)
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#define ID0_PTFS_SHIFT 24
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#define ID0_PTFS_MASK 0x2
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#define ID0_PTFS_V8_ONLY 0x2
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#define ID0_CTTW (1 << 14)
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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#define ID1_PAGESIZE (1 << 31)
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#define ID1_NUMPAGENDXB_SHIFT 28
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#define ID1_NUMPAGENDXB_MASK 7
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#define ID1_NUMS2CB_SHIFT 16
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#define ID1_NUMS2CB_MASK 0xff
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#define ID1_NUMCB_SHIFT 0
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#define ID1_NUMCB_MASK 0xff
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#define ID2_OAS_SHIFT 4
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#define ID2_OAS_MASK 0xf
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#define ID2_IAS_SHIFT 0
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#define ID2_IAS_MASK 0xf
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#define ID2_UBS_SHIFT 8
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#define ID2_UBS_MASK 0xf
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#define ID2_PTFS_4K (1 << 12)
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#define ID2_PTFS_16K (1 << 13)
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#define ID2_PTFS_64K (1 << 14)
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#define PIDR2_ARCH_SHIFT 4
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#define PIDR2_ARCH_MASK 0xf
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/* Perf Monitor registers */
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#define ARM_SMMU_GNSR0_PMCNTENSET_0 0xc00
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#define ARM_SMMU_GNSR0_PMCNTENCLR_0 0xc20
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#define ARM_SMMU_GNSR0_PMINTENSET_0 0xc40
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#define ARM_SMMU_GNSR0_PMINTENCLR_0 0xc60
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#define ARM_SMMU_GNSR0_PMOVSCLR_0 0xc80
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#define ARM_SMMU_GNSR0_PMOVSSET_0 0xcc0
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#define ARM_SMMU_GNSR0_PMCFGR_0 0xe00
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#define ARM_SMMU_GNSR0_PMCR_0 0xe04
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#define ARM_SMMU_GNSR0_PMCEID0_0 0xe20
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#define ARM_SMMU_GNSR0_PMAUTHSTATUS_0 0xfb8
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#define ARM_SMMU_GNSR0_PMDEVTYPE_0 0xfcc
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#define ARM_SMMU_GNSR0_PMEVTYPER(n) (0x400 + ((n) << 2))
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#define ARM_SMMU_GNSR0_PMEVCNTR(n) (0x0 + ((n) << 2))
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#define ARM_SMMU_GNSR0_PMCGCR(n) (0x800 + ((n) << 2))
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#define ARM_SMMU_GNSR0_PMCGSMR(n) (0xa00 + ((n) << 2))
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/* Counter group registers */
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#define PMCG_SIZE 32
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/* Event Counter registers */
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#define PMEV_SIZE 8
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/* Global TLB invalidation */
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#define ARM_SMMU_GR0_STLBIALL 0x60
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#define ARM_SMMU_GR0_TLBIVMID 0x64
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#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
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#define ARM_SMMU_GR0_TLBIALLH 0x6c
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#define ARM_SMMU_GR0_sTLBGSYNC 0x70
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#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
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#define ARM_SMMU_GR0_nsTLBGSYNC 0x470
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#define ARM_SMMU_GR0_nsTLBGSTATUS 0x474
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#define sTLBGSTATUS_GSACTIVE (1 << 0)
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#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
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/* Stream mapping registers */
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#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
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#define SMR_VALID (1 << 31)
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#define SMR_MASK_SHIFT 16
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#define SMR_MASK_MASK 0x7f80
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#define SMR_ID_SHIFT 0
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#define SMR_ID_MASK 0x7f80
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#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
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#define S2CR_CBNDX_SHIFT 0
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#define S2CR_CBNDX_MASK 0xff
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#define S2CR_TYPE_SHIFT 16
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#define S2CR_TYPE_MASK 0x3
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#define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
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#define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
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#define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
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/* Context bank attribute registers */
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#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
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#define CBAR_VMID_SHIFT 0
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#define CBAR_VMID_MASK 0xff
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#define CBAR_S1_BPSHCFG_SHIFT 8
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#define CBAR_S1_BPSHCFG_MASK 3
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#define CBAR_S1_BPSHCFG_NSH 3
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#define CBAR_S1_MEMATTR_SHIFT 12
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#define CBAR_S1_MEMATTR_MASK 0xf
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#define CBAR_S1_MEMATTR_WB 0xf
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#define CBAR_TYPE_SHIFT 16
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#define CBAR_TYPE_MASK 0x3
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#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
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#define CBAR_IRPTNDX_SHIFT 24
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#define CBAR_IRPTNDX_MASK 0xff
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#define ARM_SMMU_GR1_FRSYNRA(n) (0x400 + ((n) << 2))
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#define FRSYNRA_STREAMID_MASK 0xffff
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#define FRSYNRA_STREAMID_SHIFT 0x0
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#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
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#define CBA2R_RW64_32BIT (0 << 0)
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#define CBA2R_RW64_64BIT (1 << 0)
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/* Translation context bank */
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#define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
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#define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
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#define ARM_SMMU_CB_SCTLR 0x0
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#define ARM_SMMU_CB_RESUME 0x8
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#define ARM_SMMU_CB_TTBCR2 0x10
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#define ARM_SMMU_CB_TTBR0_LO 0x20
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#define ARM_SMMU_CB_TTBR0_HI 0x24
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#define ARM_SMMU_CB_TTBR1_LO 0x28
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#define ARM_SMMU_CB_TTBR1_HI 0x2c
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#define ARM_SMMU_CB_TTBCR 0x30
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#define ARM_SMMU_CB_CONTEXTIDR 0x34
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_FSR 0x58
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#define ARM_SMMU_CB_FAR_LO 0x60
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#define ARM_SMMU_CB_FAR_HI 0x64
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
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#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
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#define ARM_SMMU_CB_TLBSYNC 0x7f0
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#define ARM_SMMU_CB_TLBSTATUS 0x7f4
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#define SCTLR_S1_ASIDPNE (1 << 12)
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#define SCTLR_HUPCF (1 << 8)
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#define SCTLR_CFCFG (1 << 7)
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#define SCTLR_CFIE (1 << 6)
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#define SCTLR_CFRE (1 << 5)
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#define SCTLR_E (1 << 4)
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#define SCTLR_AFE (1 << 2)
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#define SCTLR_TRE (1 << 1)
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#define SCTLR_M (1 << 0)
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#define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
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#define RESUME_RETRY (0 << 0)
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#define RESUME_TERMINATE (1 << 0)
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#define TTBCR_EAE (1 << 31)
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#define TTBCR_PASIZE_SHIFT 16
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#define TTBCR_PASIZE_MASK 0x7
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#define TTBCR_TG0_4K (0 << 14)
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#define TTBCR_TG0_64K (1 << 14)
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#define TTBCR_SH0_SHIFT 12
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#define TTBCR_SH0_MASK 0x3
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#define TTBCR_SH_NS 0
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#define TTBCR_SH_OS 2
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#define TTBCR_SH_IS 3
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#define TTBCR_ORGN0_SHIFT 10
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#define TTBCR_IRGN0_SHIFT 8
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#define TTBCR_RGN_MASK 0x3
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#define TTBCR_RGN_NC 0
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#define TTBCR_RGN_WBWA 1
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#define TTBCR_RGN_WT 2
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#define TTBCR_RGN_WB 3
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#define TTBCR_SL0_SHIFT 6
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#define TTBCR_SL0_MASK 0x3
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#define TTBCR_SL0_LVL_2 0
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#define TTBCR_SL0_LVL_1 1
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#define TTBCR_T1SZ_SHIFT 16
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#define TTBCR_T0SZ_SHIFT 0
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#define TTBCR_SZ_MASK 0xf
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_MASK 0x7
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#define TTBCR2_PASIZE_SHIFT 0
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#define TTBCR2_PASIZE_MASK 0x7
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/* Common definitions for PASize and SEP fields */
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#define TTBCR2_ADDR_32 0
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#define TTBCR2_ADDR_36 1
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#define TTBCR2_ADDR_40 2
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#define TTBCR2_ADDR_42 3
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#define TTBCR2_ADDR_44 4
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#define TTBCR2_ADDR_48 5
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||
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#define TTBRn_HI_ASID_SHIFT 16
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||
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||
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#define MAIR_ATTR_SHIFT(n) ((n) << 3)
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#define MAIR_ATTR_MASK 0xff
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#define MAIR_ATTR_DEVICE 0x04
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#define MAIR_ATTR_NC 0x44
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||
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#define MAIR_ATTR_WBRWA 0xff
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||
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#define MAIR_ATTR_IDX_NC 0
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||
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#define MAIR_ATTR_IDX_CACHE 1
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#define MAIR_ATTR_IDX_DEV 2
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||
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#define FSR_MULTI (1 << 31)
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#define FSR_SS (1 << 30)
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#define FSR_UUT (1 << 8)
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#define FSR_ASF (1 << 7)
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||
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#define FSR_TLBLKF (1 << 6)
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||
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#define FSR_TLBMCF (1 << 5)
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||
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#define FSR_EF (1 << 4)
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||
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#define FSR_PF (1 << 3)
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#define FSR_AFF (1 << 2)
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||
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#define FSR_TF (1 << 1)
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||
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||
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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||
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FSR_TLBMCF | FSR_TLBLKF)
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||
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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||
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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||
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||
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#define FSYNR0_WNR (1 << 4)
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||
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||
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#endif /* _ARM_SMMU_REGS_H */
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