311 lines
11 KiB
C
311 lines
11 KiB
C
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/*
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* Freescale GPMI NAND Flash Driver
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*
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 Embedded Alley Solutions, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H
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#define __DRIVERS_MTD_NAND_GPMI_NAND_H
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#include <linux/mtd/nand.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */
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struct resources {
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void __iomem *gpmi_regs;
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void __iomem *bch_regs;
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unsigned int dma_low_channel;
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unsigned int dma_high_channel;
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struct clk *clock[GPMI_CLK_MAX];
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};
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/**
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* struct bch_geometry - BCH geometry description.
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* @gf_len: The length of Galois Field. (e.g., 13 or 14)
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* @ecc_strength: A number that describes the strength of the ECC
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* algorithm.
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* @page_size: The size, in bytes, of a physical page, including
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* both data and OOB.
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* @metadata_size: The size, in bytes, of the metadata.
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* @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
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* the first chunk in the page includes both data and
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* metadata, so it's a bit larger than this value.
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* @ecc_chunk_count: The number of ECC chunks in the page,
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* @payload_size: The size, in bytes, of the payload buffer.
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* @auxiliary_size: The size, in bytes, of the auxiliary buffer.
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* @auxiliary_status_offset: The offset into the auxiliary buffer at which
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* the ECC status appears.
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* @block_mark_byte_offset: The byte offset in the ECC-based page view at
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* which the underlying physical block mark appears.
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* @block_mark_bit_offset: The bit offset into the ECC-based page view at
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* which the underlying physical block mark appears.
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*/
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struct bch_geometry {
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unsigned int gf_len;
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unsigned int ecc_strength;
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unsigned int page_size;
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unsigned int metadata_size;
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unsigned int ecc_chunk_size;
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unsigned int ecc_chunk_count;
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unsigned int payload_size;
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unsigned int auxiliary_size;
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unsigned int auxiliary_status_offset;
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unsigned int block_mark_byte_offset;
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unsigned int block_mark_bit_offset;
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};
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/**
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* struct boot_rom_geometry - Boot ROM geometry description.
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* @stride_size_in_pages: The size of a boot block stride, in pages.
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* @search_area_stride_exponent: The logarithm to base 2 of the size of a
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* search area in boot block strides.
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*/
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struct boot_rom_geometry {
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unsigned int stride_size_in_pages;
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unsigned int search_area_stride_exponent;
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};
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/* DMA operations types */
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enum dma_ops_type {
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DMA_FOR_COMMAND = 1,
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DMA_FOR_READ_DATA,
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DMA_FOR_WRITE_DATA,
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DMA_FOR_READ_ECC_PAGE,
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DMA_FOR_WRITE_ECC_PAGE
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};
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/**
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* struct nand_timing - Fundamental timing attributes for NAND.
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* @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
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* maximum of tDS and tWP. A negative value
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* indicates this characteristic isn't known.
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* @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
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* maximum of tDH, tWH and tREH. A negative value
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* indicates this characteristic isn't known.
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* @address_setup_in_ns: The address setup time, in nanoseconds. Usually
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* the maximum of tCLS, tCS and tALS. A negative
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* value indicates this characteristic isn't known.
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* @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
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* indicates this characteristic isn't known.
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* @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
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* negative value indicates this characteristic isn't
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* known.
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* @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
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* negative value indicates this characteristic isn't
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* known.
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* @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
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* negative value indicates this characteristic isn't
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* known.
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*/
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struct nand_timing {
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int8_t data_setup_in_ns;
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int8_t data_hold_in_ns;
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int8_t address_setup_in_ns;
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int8_t gpmi_sample_delay_in_ns;
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int8_t tREA_in_ns;
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int8_t tRLOH_in_ns;
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int8_t tRHOH_in_ns;
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};
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enum gpmi_type {
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IS_MX23,
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IS_MX28,
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IS_MX6Q,
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IS_MX6SX
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};
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struct gpmi_devdata {
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enum gpmi_type type;
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int bch_max_ecc_strength;
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int max_chain_delay; /* See the async EDO mode */
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};
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struct gpmi_nand_data {
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/* flags */
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#define GPMI_ASYNC_EDO_ENABLED (1 << 0)
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#define GPMI_TIMING_INIT_OK (1 << 1)
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int flags;
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const struct gpmi_devdata *devdata;
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/* System Interface */
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struct device *dev;
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struct platform_device *pdev;
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/* Resources */
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struct resources resources;
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/* Flash Hardware */
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struct nand_timing timing;
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int timing_mode;
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/* BCH */
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struct bch_geometry bch_geometry;
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struct completion bch_done;
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/* NAND Boot issue */
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bool swap_block_mark;
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struct boot_rom_geometry rom_geometry;
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/* MTD / NAND */
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struct nand_chip nand;
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/* General-use Variables */
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int current_chip;
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unsigned int command_length;
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/* passed from upper layer */
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uint8_t *upper_buf;
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int upper_len;
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/* for DMA operations */
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bool direct_dma_map_ok;
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struct scatterlist cmd_sgl;
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char *cmd_buffer;
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struct scatterlist data_sgl;
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char *data_buffer_dma;
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void *page_buffer_virt;
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dma_addr_t page_buffer_phys;
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unsigned int page_buffer_size;
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void *payload_virt;
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dma_addr_t payload_phys;
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void *auxiliary_virt;
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dma_addr_t auxiliary_phys;
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void *raw_buffer;
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/* DMA channels */
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#define DMA_CHANS 8
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struct dma_chan *dma_chans[DMA_CHANS];
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enum dma_ops_type last_dma_type;
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enum dma_ops_type dma_type;
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struct completion dma_done;
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/* private */
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void *private;
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};
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/**
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* struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
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* @data_setup_in_cycles: The data setup time, in cycles.
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* @data_hold_in_cycles: The data hold time, in cycles.
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* @address_setup_in_cycles: The address setup time, in cycles.
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* @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
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* this value is the number of cycles multiplied
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* by 4096.
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* @use_half_periods: Indicates the clock is running slowly, so the
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* NFC DLL should use half-periods.
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* @sample_delay_factor: The sample delay factor.
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* @wrn_dly_sel: The delay on the GPMI write strobe.
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*/
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struct gpmi_nfc_hardware_timing {
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/* for HW_GPMI_TIMING0 */
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uint8_t data_setup_in_cycles;
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uint8_t data_hold_in_cycles;
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uint8_t address_setup_in_cycles;
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/* for HW_GPMI_TIMING1 */
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uint16_t device_busy_timeout;
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#define GPMI_DEFAULT_BUSY_TIMEOUT 0x500 /* default busy timeout value.*/
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/* for HW_GPMI_CTRL1 */
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bool use_half_periods;
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uint8_t sample_delay_factor;
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uint8_t wrn_dly_sel;
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};
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/**
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* struct timing_threshod - Timing threshold
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* @max_data_setup_cycles: The maximum number of data setup cycles that
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* can be expressed in the hardware.
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* @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
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* for data read internal setup. In the Reference
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* Manual, see the chapter "High-Speed NAND
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* Timing" for more details.
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* @max_sample_delay_factor: The maximum sample delay factor that can be
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* expressed in the hardware.
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* @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
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* sample delay DLL hardware can possibly work
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* with (the DLL is unusable with longer periods).
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* If the full-cycle period is greater than HALF
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* this value, the DLL must be configured to use
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* half-periods.
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* @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
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* DLL can implement.
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* @clock_frequency_in_hz: The clock frequency, in Hz, during the current
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* I/O transaction. If no I/O transaction is in
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* progress, this is the clock frequency during
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* the most recent I/O transaction.
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*/
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struct timing_threshod {
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const unsigned int max_chip_count;
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const unsigned int max_data_setup_cycles;
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const unsigned int internal_data_setup_in_ns;
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const unsigned int max_sample_delay_factor;
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const unsigned int max_dll_clock_period_in_ns;
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const unsigned int max_dll_delay_in_ns;
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unsigned long clock_frequency_in_hz;
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};
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/* Common Services */
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extern int common_nfc_set_geometry(struct gpmi_nand_data *);
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extern struct dma_chan *get_dma_chan(struct gpmi_nand_data *);
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extern void prepare_data_dma(struct gpmi_nand_data *,
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enum dma_data_direction dr);
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extern int start_dma_without_bch_irq(struct gpmi_nand_data *,
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struct dma_async_tx_descriptor *);
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extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
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struct dma_async_tx_descriptor *);
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/* GPMI-NAND helper function library */
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extern int gpmi_init(struct gpmi_nand_data *);
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extern int gpmi_extra_init(struct gpmi_nand_data *);
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extern void gpmi_clear_bch(struct gpmi_nand_data *);
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extern void gpmi_dump_info(struct gpmi_nand_data *);
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extern int bch_set_geometry(struct gpmi_nand_data *);
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extern int gpmi_is_ready(struct gpmi_nand_data *, unsigned chip);
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extern int gpmi_send_command(struct gpmi_nand_data *);
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extern void gpmi_begin(struct gpmi_nand_data *);
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extern void gpmi_end(struct gpmi_nand_data *);
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extern int gpmi_read_data(struct gpmi_nand_data *);
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extern int gpmi_send_data(struct gpmi_nand_data *);
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extern int gpmi_send_page(struct gpmi_nand_data *,
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dma_addr_t payload, dma_addr_t auxiliary);
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extern int gpmi_read_page(struct gpmi_nand_data *,
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dma_addr_t payload, dma_addr_t auxiliary);
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void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
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const u8 *src, size_t src_bit_off,
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size_t nbits);
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/* BCH : Status Block Completion Codes */
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#define STATUS_GOOD 0x00
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#define STATUS_ERASED 0xff
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#define STATUS_UNCORRECTABLE 0xfe
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/* Use the devdata to distinguish different Archs. */
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#define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23)
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#define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28)
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#define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q)
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#define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
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#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x))
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#endif
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