490 lines
15 KiB
C
490 lines
15 KiB
C
/*
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* drivers/media/i2c/smiapp-pll.c
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*
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* Generic driver for SMIA/SMIA++ compliant camera modules
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*
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* Copyright (C) 2011--2012 Nokia Corporation
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* Contact: Sakari Ailus <sakari.ailus@iki.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/device.h>
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#include <linux/gcd.h>
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#include <linux/lcm.h>
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#include <linux/module.h>
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#include "smiapp-pll.h"
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/* Return an even number or one. */
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static inline uint32_t clk_div_even(uint32_t a)
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{
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return max_t(uint32_t, 1, a & ~1);
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}
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/* Return an even number or one. */
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static inline uint32_t clk_div_even_up(uint32_t a)
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{
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if (a == 1)
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return 1;
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return (a + 1) & ~1;
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}
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static inline uint32_t is_one_or_even(uint32_t a)
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{
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if (a == 1)
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return 1;
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if (a & 1)
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return 0;
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return 1;
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}
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static int bounds_check(struct device *dev, uint32_t val,
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uint32_t min, uint32_t max, char *str)
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{
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if (val >= min && val <= max)
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return 0;
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dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
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return -EINVAL;
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}
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static void print_pll(struct device *dev, struct smiapp_pll *pll)
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{
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dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
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dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
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if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
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dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
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dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
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}
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dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
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dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
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dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
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dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
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dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
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if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
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dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
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pll->op.sys_clk_freq_hz);
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dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
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pll->op.pix_clk_freq_hz);
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}
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dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
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dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
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}
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static int check_all_bounds(struct device *dev,
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const struct smiapp_pll_limits *limits,
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const struct smiapp_pll_branch_limits *op_limits,
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struct smiapp_pll *pll,
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struct smiapp_pll_branch *op_pll)
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{
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int rval;
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rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
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limits->min_pll_ip_freq_hz,
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limits->max_pll_ip_freq_hz,
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"pll_ip_clk_freq_hz");
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if (!rval)
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rval = bounds_check(
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dev, pll->pll_multiplier,
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limits->min_pll_multiplier, limits->max_pll_multiplier,
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"pll_multiplier");
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if (!rval)
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rval = bounds_check(
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dev, pll->pll_op_clk_freq_hz,
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limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
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"pll_op_clk_freq_hz");
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if (!rval)
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rval = bounds_check(
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dev, op_pll->sys_clk_div,
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op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
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"op_sys_clk_div");
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if (!rval)
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rval = bounds_check(
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dev, op_pll->sys_clk_freq_hz,
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op_limits->min_sys_clk_freq_hz,
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op_limits->max_sys_clk_freq_hz,
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"op_sys_clk_freq_hz");
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if (!rval)
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rval = bounds_check(
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dev, op_pll->pix_clk_freq_hz,
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op_limits->min_pix_clk_freq_hz,
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op_limits->max_pix_clk_freq_hz,
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"op_pix_clk_freq_hz");
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/*
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* If there are no OP clocks, the VT clocks are contained in
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* the OP clock struct.
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*/
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if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
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return rval;
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if (!rval)
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rval = bounds_check(
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dev, pll->vt.sys_clk_freq_hz,
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limits->vt.min_sys_clk_freq_hz,
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limits->vt.max_sys_clk_freq_hz,
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"vt_sys_clk_freq_hz");
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if (!rval)
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rval = bounds_check(
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dev, pll->vt.pix_clk_freq_hz,
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limits->vt.min_pix_clk_freq_hz,
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limits->vt.max_pix_clk_freq_hz,
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"vt_pix_clk_freq_hz");
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return rval;
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}
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/*
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* Heuristically guess the PLL tree for a given common multiplier and
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* divisor. Begin with the operational timing and continue to video
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* timing once operational timing has been verified.
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*
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* @mul is the PLL multiplier and @div is the common divisor
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* (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
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* multiplier will be a multiple of @mul.
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*
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* @return Zero on success, error code on error.
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*/
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static int __smiapp_pll_calculate(
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struct device *dev, const struct smiapp_pll_limits *limits,
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const struct smiapp_pll_branch_limits *op_limits,
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struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
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uint32_t div, uint32_t lane_op_clock_ratio)
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{
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uint32_t sys_div;
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uint32_t best_pix_div = INT_MAX >> 1;
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uint32_t vt_op_binning_div;
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/*
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* Higher multipliers (and divisors) are often required than
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* necessitated by the external clock and the output clocks.
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* There are limits for all values in the clock tree. These
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* are the minimum and maximum multiplier for mul.
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*/
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uint32_t more_mul_min, more_mul_max;
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uint32_t more_mul_factor;
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uint32_t min_vt_div, max_vt_div, vt_div;
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uint32_t min_sys_div, max_sys_div;
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unsigned int i;
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/*
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* Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
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* too high.
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*/
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dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
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/* Don't go above max pll multiplier. */
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more_mul_max = limits->max_pll_multiplier / mul;
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dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
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more_mul_max);
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/* Don't go above max pll op frequency. */
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more_mul_max =
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min_t(uint32_t,
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more_mul_max,
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limits->max_pll_op_freq_hz
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/ (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
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dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
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more_mul_max);
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/* Don't go above the division capability of op sys clock divider. */
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more_mul_max = min(more_mul_max,
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op_limits->max_sys_clk_div * pll->pre_pll_clk_div
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/ div);
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dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
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more_mul_max);
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/* Ensure we won't go above min_pll_multiplier. */
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more_mul_max = min(more_mul_max,
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DIV_ROUND_UP(limits->max_pll_multiplier, mul));
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dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
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more_mul_max);
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/* Ensure we won't go below min_pll_op_freq_hz. */
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more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
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pll->ext_clk_freq_hz / pll->pre_pll_clk_div
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* mul);
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dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
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more_mul_min);
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/* Ensure we won't go below min_pll_multiplier. */
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more_mul_min = max(more_mul_min,
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DIV_ROUND_UP(limits->min_pll_multiplier, mul));
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dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
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more_mul_min);
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if (more_mul_min > more_mul_max) {
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dev_dbg(dev,
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"unable to compute more_mul_min and more_mul_max\n");
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return -EINVAL;
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}
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more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
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dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
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more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
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dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
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more_mul_factor);
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i = roundup(more_mul_min, more_mul_factor);
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if (!is_one_or_even(i))
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i <<= 1;
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dev_dbg(dev, "final more_mul: %u\n", i);
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if (i > more_mul_max) {
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dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
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return -EINVAL;
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}
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pll->pll_multiplier = mul * i;
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op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
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dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
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pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
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/ pll->pre_pll_clk_div;
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pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
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* pll->pll_multiplier;
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/* Derive pll_op_clk_freq_hz. */
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op_pll->sys_clk_freq_hz =
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pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
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op_pll->pix_clk_div = pll->bits_per_pixel;
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dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
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op_pll->pix_clk_freq_hz =
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op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
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if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
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/* No OP clocks --- VT clocks are used instead. */
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goto out_skip_vt_calc;
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}
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/*
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* Some sensors perform analogue binning and some do this
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* digitally. The ones doing this digitally can be roughly be
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* found out using this formula. The ones doing this digitally
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* should run at higher clock rate, so smaller divisor is used
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* on video timing side.
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*/
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if (limits->min_line_length_pck_bin > limits->min_line_length_pck
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/ pll->binning_horizontal)
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vt_op_binning_div = pll->binning_horizontal;
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else
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vt_op_binning_div = 1;
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dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
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/*
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* Profile 2 supports vt_pix_clk_div E [4, 10]
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*
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* Horizontal binning can be used as a base for difference in
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* divisors. One must make sure that horizontal blanking is
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* enough to accommodate the CSI-2 sync codes.
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*
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* Take scaling factor into account as well.
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*
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* Find absolute limits for the factor of vt divider.
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*/
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dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
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min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
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* pll->scale_n,
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lane_op_clock_ratio * vt_op_binning_div
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* pll->scale_m);
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/* Find smallest and biggest allowed vt divisor. */
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dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
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min_vt_div = max(min_vt_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.max_pix_clk_freq_hz));
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dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
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min_vt_div);
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min_vt_div = max_t(uint32_t, min_vt_div,
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limits->vt.min_pix_clk_div
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* limits->vt.min_sys_clk_div);
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dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
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max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
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dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
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max_vt_div = min(max_vt_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
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max_vt_div);
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/*
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* Find limitsits for sys_clk_div. Not all values are possible
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* with all values of pix_clk_div.
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*/
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min_sys_div = limits->vt.min_sys_clk_div;
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dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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DIV_ROUND_UP(min_vt_div,
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limits->vt.max_pix_clk_div));
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dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
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min_sys_div = max(min_sys_div,
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pll->pll_op_clk_freq_hz
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/ limits->vt.max_sys_clk_freq_hz);
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dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
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min_sys_div = clk_div_even_up(min_sys_div);
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dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
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max_sys_div = limits->vt.max_sys_clk_div;
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dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(max_vt_div,
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limits->vt.min_pix_clk_div));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
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max_sys_div = min(max_sys_div,
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DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
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limits->vt.min_pix_clk_freq_hz));
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dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
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/*
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* Find pix_div such that a legal pix_div * sys_div results
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* into a value which is not smaller than div, the desired
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* divisor.
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*/
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for (vt_div = min_vt_div; vt_div <= max_vt_div;
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vt_div += 2 - (vt_div & 1)) {
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for (sys_div = min_sys_div;
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sys_div <= max_sys_div;
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sys_div += 2 - (sys_div & 1)) {
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uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
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if (pix_div < limits->vt.min_pix_clk_div
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|| pix_div > limits->vt.max_pix_clk_div) {
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dev_dbg(dev,
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"pix_div %u too small or too big (%u--%u)\n",
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pix_div,
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limits->vt.min_pix_clk_div,
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limits->vt.max_pix_clk_div);
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continue;
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}
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/* Check if this one is better. */
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if (pix_div * sys_div
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<= roundup(min_vt_div, best_pix_div))
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best_pix_div = pix_div;
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}
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if (best_pix_div < INT_MAX >> 1)
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break;
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}
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pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
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pll->vt.pix_clk_div = best_pix_div;
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pll->vt.sys_clk_freq_hz =
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pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
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pll->vt.pix_clk_freq_hz =
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pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
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out_skip_vt_calc:
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pll->pixel_rate_csi =
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op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
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pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
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return check_all_bounds(dev, limits, op_limits, pll, op_pll);
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}
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int smiapp_pll_calculate(struct device *dev,
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const struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll)
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{
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const struct smiapp_pll_branch_limits *op_limits = &limits->op;
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struct smiapp_pll_branch *op_pll = &pll->op;
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uint16_t min_pre_pll_clk_div;
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uint16_t max_pre_pll_clk_div;
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uint32_t lane_op_clock_ratio;
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uint32_t mul, div;
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unsigned int i;
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int rval = -EINVAL;
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if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
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/*
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* If there's no OP PLL at all, use the VT values
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* instead. The OP values are ignored for the rest of
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* the PLL calculation.
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*/
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op_limits = &limits->vt;
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op_pll = &pll->vt;
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}
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if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
|
|
lane_op_clock_ratio = pll->csi2.lanes;
|
|
else
|
|
lane_op_clock_ratio = 1;
|
|
dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
|
|
|
|
dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
|
|
pll->binning_vertical);
|
|
|
|
switch (pll->bus_type) {
|
|
case SMIAPP_PLL_BUS_TYPE_CSI2:
|
|
/* CSI transfers 2 bits per clock per lane; thus times 2 */
|
|
pll->pll_op_clk_freq_hz = pll->link_freq * 2
|
|
* (pll->csi2.lanes / lane_op_clock_ratio);
|
|
break;
|
|
case SMIAPP_PLL_BUS_TYPE_PARALLEL:
|
|
pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
|
|
/ DIV_ROUND_UP(pll->bits_per_pixel,
|
|
pll->parallel.bus_width);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Figure out limits for pre-pll divider based on extclk */
|
|
dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
|
|
limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
|
|
max_pre_pll_clk_div =
|
|
min_t(uint16_t, limits->max_pre_pll_clk_div,
|
|
clk_div_even(pll->ext_clk_freq_hz /
|
|
limits->min_pll_ip_freq_hz));
|
|
min_pre_pll_clk_div =
|
|
max_t(uint16_t, limits->min_pre_pll_clk_div,
|
|
clk_div_even_up(
|
|
DIV_ROUND_UP(pll->ext_clk_freq_hz,
|
|
limits->max_pll_ip_freq_hz)));
|
|
dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
|
|
min_pre_pll_clk_div, max_pre_pll_clk_div);
|
|
|
|
i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
|
|
mul = div_u64(pll->pll_op_clk_freq_hz, i);
|
|
div = pll->ext_clk_freq_hz / i;
|
|
dev_dbg(dev, "mul %u / div %u\n", mul, div);
|
|
|
|
min_pre_pll_clk_div =
|
|
max_t(uint16_t, min_pre_pll_clk_div,
|
|
clk_div_even_up(
|
|
DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
|
|
limits->max_pll_op_freq_hz)));
|
|
dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
|
|
min_pre_pll_clk_div, max_pre_pll_clk_div);
|
|
|
|
for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
|
|
pll->pre_pll_clk_div <= max_pre_pll_clk_div;
|
|
pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
|
|
rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
|
|
op_pll, mul, div,
|
|
lane_op_clock_ratio);
|
|
if (rval)
|
|
continue;
|
|
|
|
print_pll(dev, pll);
|
|
return 0;
|
|
}
|
|
|
|
dev_info(dev, "unable to compute pre_pll divisor\n");
|
|
return rval;
|
|
}
|
|
EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
|
|
|
|
MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
|
|
MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
|
|
MODULE_LICENSE("GPL");
|