257 lines
7.3 KiB
C
257 lines
7.3 KiB
C
/*
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* drivers/video/tegra/host/host1x/host1x_debug.c
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*
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* Copyright (C) 2010 Google, Inc.
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* Author: Erik Gilling <konkers@android.com>
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*
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* Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <linux/mm.h>
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#include <linux/scatterlist.h>
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#include <linux/io.h>
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#include "dev.h"
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#include "debug.h"
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#include "nvhost_cdma.h"
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#include "nvhost_channel.h"
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#include "nvhost_job.h"
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#include "chip_support.h"
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#define NVHOST_DEBUG_MAX_PAGE_OFFSET 102400
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enum {
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NVHOST_DBG_STATE_CMD = 0,
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NVHOST_DBG_STATE_DATA = 1,
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NVHOST_DBG_STATE_GATHER = 2
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};
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static void do_show_channel_gather(struct output *o,
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phys_addr_t phys_addr,
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u32 words, struct nvhost_cdma *cdma,
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phys_addr_t pin_addr, u32 *map_addr)
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{
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/* Map dmaget cursor to corresponding nvmap_handle */
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u32 offset;
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int state, i;
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offset = phys_addr - pin_addr;
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/*
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* Sometimes we're given different hardware address to the same
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* page - in these cases the offset will get an invalid number and
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* we just have to bail out.
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*/
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if (offset > NVHOST_DEBUG_MAX_PAGE_OFFSET) {
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nvhost_debug_output(o, "[address mismatch]\n");
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} else {
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/* GATHER buffer starts always with commands */
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state = NVHOST_DBG_STATE_CMD;
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for (i = 0; i < words; i++)
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nvhost_debug_output(o,
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"%08x ", *(map_addr + offset/4 + i));
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nvhost_debug_output(o, "\n");
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}
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}
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static void show_channel_gathers(struct output *o, struct nvhost_cdma *cdma)
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{
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struct nvhost_job *job;
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int i;
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mutex_lock(&cdma->sync_queue_lock);
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if (list_empty(&cdma->sync_queue)) {
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mutex_unlock(&cdma->sync_queue_lock);
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nvhost_debug_output(o, "The CDMA sync queue is empty.\n");
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return;
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}
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job = list_first_entry(&cdma->sync_queue, struct nvhost_job, list);
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mutex_unlock(&cdma->sync_queue_lock);
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nvhost_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d, num_slots=%d, num_handles=%d\n",
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job,
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job->sp ? job->sp->id : -1,
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job->sp ? job->sp->fence : -1,
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job->first_get,
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job->timeout,
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job->num_slots,
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job->num_unpins);
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for (i = 0; i < job->num_gathers; i++) {
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struct nvhost_job_gather *g = &job->gathers[i];
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u32 *mapped = dma_buf_vmap(g->buf);
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if (!mapped) {
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nvhost_debug_output(o, "[could not mmap]\n");
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continue;
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}
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nvhost_debug_output(o,
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" GATHER at %08llx+%04x, %u words\n",
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(u64)g->mem_base, g->offset, g->words);
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do_show_channel_gather(o, g->mem_base + g->offset,
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g->words, cdma, g->mem_base, mapped);
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dma_buf_vunmap(g->buf, mapped);
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}
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}
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static void t20_debug_show_channel_cdma(struct nvhost_master *m,
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struct nvhost_channel *ch, struct output *o, int chid)
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{
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struct nvhost_channel *channel = ch;
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struct nvhost_cdma *cdma = &channel->cdma;
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u32 dmaput, dmaget, dmactrl;
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u32 cbstat, cbread, cmdstat;
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u32 val, base, baseval;
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dmaput = host1x_channel_readl(channel, host1x_channel_dmaput_r());
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dmaget = host1x_channel_readl(channel, host1x_channel_dmaget_r());
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dmactrl = host1x_channel_readl(channel, host1x_channel_dmactrl_r());
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cbread = host1x_sync_readl(m, host1x_sync_cbread0_r() + 4 * chid);
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cbstat = host1x_sync_readl(m, host1x_sync_cbstat_0_r() + 4 * chid);
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cmdstat = host1x_sync_readl(m, host1x_sync_cmdproc_stat_r());
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#ifdef CONFIG_PM
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nvhost_debug_output(o, "%d-%s (%d): ", chid,
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channel->dev->name,
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atomic_read(&channel->dev->dev.power.usage_count));
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#else
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nvhost_debug_output(o, "%d-%s: ", chid, channel->dev->name);
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#endif
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if (host1x_channel_dmactrl_dmastop_v(dmactrl)
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|| !channel->cdma.push_buffer.mapped) {
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nvhost_debug_output(o, "inactive\n\n");
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return;
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}
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if (cmdstat & BIT(chid))
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nvhost_debug_output(o, "bad opcode observed, ");
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switch (cbstat) {
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case 0x00010008:
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nvhost_debug_output(o, "waiting on syncpt %d val %d\n",
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cbread >> 24, cbread & 0xffffff);
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break;
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case 0x00010009:
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base = (cbread >> 16) & 0xff;
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baseval = host1x_sync_readl(m,
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host1x_sync_syncpt_base_0_r() + 4 * base);
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val = cbread & 0xffff;
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nvhost_debug_output(o, "waiting on syncpt %d val %d "
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"(base %d = %d; offset = %d)\n",
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cbread >> 24, baseval + val,
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base, baseval, val);
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break;
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default:
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nvhost_debug_output(o,
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"active class %02x, offset %04x, val %08x\n",
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host1x_sync_cbstat_0_cbclass0_v(cbstat),
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host1x_sync_cbstat_0_cboffset0_v(cbstat),
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cbread);
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break;
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}
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nvhost_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
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dmaput, dmaget, dmactrl);
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nvhost_debug_output(o, "CBREAD %08x, CBSTAT %08x\n", cbread, cbstat);
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show_channel_gathers(o, cdma);
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nvhost_debug_output(o, "\n");
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}
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static void t20_debug_show_channel_fifo(struct nvhost_master *m,
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struct nvhost_channel *ch, struct output *o, int chid)
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{
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u32 val, rd_ptr, wr_ptr, start, end, max = 64;
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struct nvhost_channel *channel = ch;
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nvhost_debug_output(o, "%d: fifo:\n", chid);
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host1x_sync_writel(m, host1x_sync_cfpeek_ctrl_r(),
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host1x_sync_cfpeek_ctrl_cfpeek_ena_f(1)
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| host1x_sync_cfpeek_ctrl_cfpeek_channr_f(chid));
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wmb();
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val = host1x_channel_readl(channel, host1x_channel_fifostat_r());
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if (host1x_channel_fifostat_cfempty_v(val)) {
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host1x_sync_writel(m, host1x_sync_cfpeek_ctrl_r(), 0x0);
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nvhost_debug_output(o, "FIFOSTAT %08x\n[empty]\n",
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val);
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return;
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}
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val = host1x_sync_readl(m, host1x_sync_cfpeek_ptrs_r());
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rd_ptr = host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(val);
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wr_ptr = host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(val);
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val = host1x_sync_readl(m, host1x_sync_cf0_setup_r() + 4 * chid);
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start = host1x_sync_cf0_setup_cf0_base_v(val);
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end = host1x_sync_cf0_setup_cf0_limit_v(val);
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nvhost_debug_output(o, "FIFOSTAT %08x, %03x - %03x, RD %03x, WR %03x\n",
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val, start, end, rd_ptr, wr_ptr);
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do {
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host1x_sync_writel(m, host1x_sync_cfpeek_ctrl_r(),
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host1x_sync_cfpeek_ctrl_cfpeek_ena_f(1)
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| host1x_sync_cfpeek_ctrl_cfpeek_channr_f(chid)
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| host1x_sync_cfpeek_ctrl_cfpeek_addr_f(rd_ptr));
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wmb();
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val = host1x_sync_readl(m, host1x_sync_cfpeek_read_r());
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rmb();
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nvhost_debug_output(o, "%08x ", val);
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if (rd_ptr == end)
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rd_ptr = start;
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else
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rd_ptr++;
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max--;
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} while (max && rd_ptr != wr_ptr);
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nvhost_debug_output(o, "\n");
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host1x_sync_writel(m, host1x_sync_cfpeek_ctrl_r(), 0x0);
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}
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static void t20_debug_show_mlocks(struct nvhost_master *m, struct output *o)
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{
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int i;
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nvhost_debug_output(o, "---- mlocks ----\n");
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for (i = 0; i < NV_HOST1X_NB_MLOCKS; i++) {
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u32 owner = host1x_sync_readl(m,
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host1x_sync_mlock_owner_0_r() + i * 4);
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if (host1x_sync_mlock_owner_0_mlock_ch_owns_0_v(owner))
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nvhost_debug_output(o, "%d: locked by channel %d\n",
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i,
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host1x_sync_mlock_owner_0_mlock_owner_chid_0_v(
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owner));
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else if (host1x_sync_mlock_owner_0_mlock_cpu_owns_0_v(owner))
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nvhost_debug_output(o, "%d: locked by cpu\n", i);
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}
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nvhost_debug_output(o, "\n");
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}
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static const struct nvhost_debug_ops host1x_debug_ops = {
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.show_channel_cdma = t20_debug_show_channel_cdma,
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.show_channel_fifo = t20_debug_show_channel_fifo,
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.show_mlocks = t20_debug_show_mlocks,
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};
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