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Merge upstream changes from Marlin 2.1.2

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This commit is contained in:
Stefan Kalscheuer
2022-12-19 15:23:45 +01:00
parent fe9ea826a5
commit 67c7ce7b79
427 changed files with 10732 additions and 7834 deletions
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148
buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/board.cpp
View File

@@ -131,74 +131,74 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
{&gpioc, NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN */
{&gpioc, NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT */
{&gpiod, NULL, NULL, 0, 0, ADCx} , /* PD0 OSC_IN */
{&gpiod, NULL, NULL, 1, 0, ADCx} , /* PD1 OSC_OUT */
{&gpiod, NULL, NULL, 2, 0, ADCx} , /* PD2 TIM3_ETR/UART5_RX SDIO_CMD */
{&gpiod, NULL, NULL, 0, 0, ADCx} , /* PD0 OSC_IN */
{&gpiod, NULL, NULL, 1, 0, ADCx} , /* PD1 OSC_OUT */
{&gpiod, NULL, NULL, 2, 0, ADCx} , /* PD2 TIM3_ETR/UART5_RX SDIO_CMD */
{&gpiod, NULL, NULL, 3, 0, ADCx} , /* PD3 FSMC_CLK */
{&gpiod, NULL, NULL, 4, 0, ADCx} , /* PD4 FSMC_NOE */
{&gpiod, NULL, NULL, 5, 0, ADCx} , /* PD5 FSMC_NWE */
{&gpiod, NULL, NULL, 6, 0, ADCx} , /* PD6 FSMC_NWAIT */
{&gpiod, NULL, NULL, 7, 0, ADCx} , /* PD7 FSMC_NE1/FSMC_NCE2 */
{&gpiod, NULL, NULL, 8, 0, ADCx} , /* PD8 FSMC_D13 */
{&gpiod, NULL, NULL, 9, 0, ADCx} , /* PD9 FSMC_D14 */
{&gpiod, NULL, NULL, 10, 0, ADCx} , /* PD10 FSMC_D15 */
{&gpiod, NULL, NULL, 11, 0, ADCx} , /* PD11 FSMC_A16 */
{&gpiod, NULL, NULL, 12, 0, ADCx} , /* PD12 FSMC_A17 */
{&gpiod, NULL, NULL, 13, 0, ADCx} , /* PD13 FSMC_A18 */
{&gpiod, NULL, NULL, 14, 0, ADCx} , /* PD14 FSMC_D0 */
{&gpiod, NULL, NULL, 15, 0, ADCx} , /* PD15 FSMC_D1 */
{&gpiod, NULL, NULL, 3, 0, ADCx} , /* PD3 FSMC_CLK */
{&gpiod, NULL, NULL, 4, 0, ADCx} , /* PD4 FSMC_NOE */
{&gpiod, NULL, NULL, 5, 0, ADCx} , /* PD5 FSMC_NWE */
{&gpiod, NULL, NULL, 6, 0, ADCx} , /* PD6 FSMC_NWAIT */
{&gpiod, NULL, NULL, 7, 0, ADCx} , /* PD7 FSMC_NE1/FSMC_NCE2 */
{&gpiod, NULL, NULL, 8, 0, ADCx} , /* PD8 FSMC_D13 */
{&gpiod, NULL, NULL, 9, 0, ADCx} , /* PD9 FSMC_D14 */
{&gpiod, NULL, NULL, 10, 0, ADCx} , /* PD10 FSMC_D15 */
{&gpiod, NULL, NULL, 11, 0, ADCx} , /* PD11 FSMC_A16 */
{&gpiod, NULL, NULL, 12, 0, ADCx} , /* PD12 FSMC_A17 */
{&gpiod, NULL, NULL, 13, 0, ADCx} , /* PD13 FSMC_A18 */
{&gpiod, NULL, NULL, 14, 0, ADCx} , /* PD14 FSMC_D0 */
{&gpiod, NULL, NULL, 15, 0, ADCx} , /* PD15 FSMC_D1 */
{&gpioe, NULL, NULL, 0, 0, ADCx} , /* PE0 */
{&gpioe, NULL, NULL, 1, 0, ADCx} , /* PE1 */
{&gpioe, NULL, NULL, 2, 0, ADCx} , /* PE2 */
{&gpioe, NULL, NULL, 3, 0, ADCx} , /* PE3 */
{&gpioe, NULL, NULL, 4, 0, ADCx} , /* PE4 */
{&gpioe, NULL, NULL, 5, 0, ADCx} , /* PE5 */
{&gpioe, NULL, NULL, 6, 0, ADCx} , /* PE6 */
{&gpioe, NULL, NULL, 7, 0, ADCx} , /* PE7 */
{&gpioe, NULL, NULL, 8, 0, ADCx} , /* PE8 */
{&gpioe, NULL, NULL, 9, 0, ADCx} , /* PE9 */
{&gpioe, NULL, NULL, 10, 0, ADCx} , /* PE10 */
{&gpioe, NULL, NULL, 11, 0, ADCx} , /* PE11 */
{&gpioe, NULL, NULL, 12, 0, ADCx} , /* PE12 */
{&gpioe, NULL, NULL, 13, 0, ADCx} , /* PE13 */
{&gpioe, NULL, NULL, 14, 0, ADCx} , /* PE14 */
{&gpioe, NULL, NULL, 15, 0, ADCx} , /* PE15 */
{&gpioe, NULL, NULL, 0, 0, ADCx} , /* PE0 */
{&gpioe, NULL, NULL, 1, 0, ADCx} , /* PE1 */
{&gpioe, NULL, NULL, 2, 0, ADCx} , /* PE2 */
{&gpioe, NULL, NULL, 3, 0, ADCx} , /* PE3 */
{&gpioe, NULL, NULL, 4, 0, ADCx} , /* PE4 */
{&gpioe, NULL, NULL, 5, 0, ADCx} , /* PE5 */
{&gpioe, NULL, NULL, 6, 0, ADCx} , /* PE6 */
{&gpioe, NULL, NULL, 7, 0, ADCx} , /* PE7 */
{&gpioe, NULL, NULL, 8, 0, ADCx} , /* PE8 */
{&gpioe, NULL, NULL, 9, 0, ADCx} , /* PE9 */
{&gpioe, NULL, NULL, 10, 0, ADCx} , /* PE10 */
{&gpioe, NULL, NULL, 11, 0, ADCx} , /* PE11 */
{&gpioe, NULL, NULL, 12, 0, ADCx} , /* PE12 */
{&gpioe, NULL, NULL, 13, 0, ADCx} , /* PE13 */
{&gpioe, NULL, NULL, 14, 0, ADCx} , /* PE14 */
{&gpioe, NULL, NULL, 15, 0, ADCx} , /* PE15 */
{&gpiof, NULL, NULL, 0, 0, ADCx} , /* PF0 */
{&gpiof, NULL, NULL, 1, 0, ADCx} , /* PF1 */
{&gpiof, NULL, NULL, 2, 0, ADCx} , /* PF2 */
{&gpiof, NULL, NULL, 3, 0, ADCx} , /* PF3 */
{&gpiof, NULL, NULL, 4, 0, ADCx} , /* PF4 */
{&gpiof, NULL, NULL, 5, 0, ADCx} , /* PF5 */
{&gpiof, NULL, NULL, 6, 0, ADCx} , /* PF6 */
{&gpiof, NULL, NULL, 7, 0, ADCx} , /* PF7 */
{&gpiof, NULL, NULL, 8, 0, ADCx} , /* PF8 */
{&gpiof, NULL, NULL, 9, 0, ADCx} , /* PF9 */
{&gpiof, NULL, NULL, 10, 0, ADCx} , /* PF10 */
{&gpiof, NULL, NULL, 11, 0, ADCx} , /* PF11 */
{&gpiof, NULL, NULL, 12, 0, ADCx} , /* PF12 */
{&gpiof, NULL, NULL, 13, 0, ADCx} , /* PF13 */
{&gpiof, NULL, NULL, 14, 0, ADCx} , /* PF14 */
{&gpiof, NULL, NULL, 15, 0, ADCx} , /* PF15 */
{&gpiof, NULL, NULL, 0, 0, ADCx} , /* PF0 */
{&gpiof, NULL, NULL, 1, 0, ADCx} , /* PF1 */
{&gpiof, NULL, NULL, 2, 0, ADCx} , /* PF2 */
{&gpiof, NULL, NULL, 3, 0, ADCx} , /* PF3 */
{&gpiof, NULL, NULL, 4, 0, ADCx} , /* PF4 */
{&gpiof, NULL, NULL, 5, 0, ADCx} , /* PF5 */
{&gpiof, NULL, NULL, 6, 0, ADCx} , /* PF6 */
{&gpiof, NULL, NULL, 7, 0, ADCx} , /* PF7 */
{&gpiof, NULL, NULL, 8, 0, ADCx} , /* PF8 */
{&gpiof, NULL, NULL, 9, 0, ADCx} , /* PF9 */
{&gpiof, NULL, NULL, 10, 0, ADCx} , /* PF10 */
{&gpiof, NULL, NULL, 11, 0, ADCx} , /* PF11 */
{&gpiof, NULL, NULL, 12, 0, ADCx} , /* PF12 */
{&gpiof, NULL, NULL, 13, 0, ADCx} , /* PF13 */
{&gpiof, NULL, NULL, 14, 0, ADCx} , /* PF14 */
{&gpiof, NULL, NULL, 15, 0, ADCx} , /* PF15 */
{&gpiog, NULL, NULL, 0, 0, ADCx} , /* PG0 */
{&gpiog, NULL, NULL, 1, 0, ADCx} , /* PG1 */
{&gpiog, NULL, NULL, 2, 0, ADCx} , /* PG2 */
{&gpiog, NULL, NULL, 3, 0, ADCx} , /* PG3 */
{&gpiog, NULL, NULL, 4, 0, ADCx} , /* PG4 */
{&gpiog, NULL, NULL, 5, 0, ADCx} , /* PG5 */
{&gpiog, NULL, NULL, 6, 0, ADCx} , /* PG6 */
{&gpiog, NULL, NULL, 7, 0, ADCx} , /* PG7 */
{&gpiog, NULL, NULL, 8, 0, ADCx} , /* PG8 */
{&gpiog, NULL, NULL, 9, 0, ADCx} , /* PG9 */
{&gpiog, NULL, NULL, 10, 0, ADCx} , /* PG10 */
{&gpiog, NULL, NULL, 11, 0, ADCx} , /* PG11 */
{&gpiog, NULL, NULL, 12, 0, ADCx} , /* PG12 */
{&gpiog, NULL, NULL, 13, 0, ADCx} , /* PG13 */
{&gpiog, NULL, NULL, 14, 0, ADCx} , /* PG14 */
{&gpiog, NULL, NULL, 15, 0, ADCx} /* PG15 */
{&gpiog, NULL, NULL, 0, 0, ADCx} , /* PG0 */
{&gpiog, NULL, NULL, 1, 0, ADCx} , /* PG1 */
{&gpiog, NULL, NULL, 2, 0, ADCx} , /* PG2 */
{&gpiog, NULL, NULL, 3, 0, ADCx} , /* PG3 */
{&gpiog, NULL, NULL, 4, 0, ADCx} , /* PG4 */
{&gpiog, NULL, NULL, 5, 0, ADCx} , /* PG5 */
{&gpiog, NULL, NULL, 6, 0, ADCx} , /* PG6 */
{&gpiog, NULL, NULL, 7, 0, ADCx} , /* PG7 */
{&gpiog, NULL, NULL, 8, 0, ADCx} , /* PG8 */
{&gpiog, NULL, NULL, 9, 0, ADCx} , /* PG9 */
{&gpiog, NULL, NULL, 10, 0, ADCx} , /* PG10 */
{&gpiog, NULL, NULL, 11, 0, ADCx} , /* PG11 */
{&gpiog, NULL, NULL, 12, 0, ADCx} , /* PG12 */
{&gpiog, NULL, NULL, 13, 0, ADCx} , /* PG13 */
{&gpiog, NULL, NULL, 14, 0, ADCx} , /* PG14 */
{&gpiog, NULL, NULL, 15, 0, ADCx} /* PG15 */
};
/* Basically everything that is defined as having a timer us PWM */
@@ -219,15 +219,15 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
#ifdef SERIAL_USB
DEFINE_HWSERIAL(Serial1, 1);
DEFINE_HWSERIAL(Serial2, 2);
DEFINE_HWSERIAL(Serial3, 3);
DEFINE_HWSERIAL_UART(Serial4, 4);
DEFINE_HWSERIAL_UART(Serial5, 5);
DEFINE_HWSERIAL(Serial1, 1);
DEFINE_HWSERIAL(Serial2, 2);
DEFINE_HWSERIAL(Serial3, 3);
DEFINE_HWSERIAL_UART(Serial4, 4);
DEFINE_HWSERIAL_UART(Serial5, 5);
#else
DEFINE_HWSERIAL(Serial, 1);
DEFINE_HWSERIAL(Serial1, 2);
DEFINE_HWSERIAL(Serial2, 3);
DEFINE_HWSERIAL_UART(Serial3, 4);
DEFINE_HWSERIAL_UART(Serial4, 5);
DEFINE_HWSERIAL(Serial, 1);
DEFINE_HWSERIAL(Serial1, 2);
DEFINE_HWSERIAL(Serial2, 3);
DEFINE_HWSERIAL_UART(Serial3, 4);
DEFINE_HWSERIAL_UART(Serial4, 5);
#endif

2
buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/board/board.h
View File

@@ -63,7 +63,6 @@
* SPI3 is unusable due to pin 43 (PB4) and NRST tie-together :(, but
* leave the definitions so as not to clutter things up. This is only
* OK since RET6 Ed. is specifically advertised as a beta board. */
#define BOARD_NR_SPI 3
#define BOARD_SPI1_NSS_PIN PA4
#define BOARD_SPI1_SCK_PIN PA5
#define BOARD_SPI1_MISO_PIN PA6
@@ -79,7 +78,6 @@
#define BOARD_SPI3_MISO_PIN PB4
#define BOARD_SPI3_MOSI_PIN PB5
/* GPIO A to E = 5 * 16 - BOOT1 not used = 79*/
#define BOARD_NR_GPIO_PINS 112
/* Note: NOT 19. The missing one is D38 a.k.a. BOARD_BUTTON_PIN, which

6
buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/wirish/boards.cpp
View File

@@ -144,10 +144,10 @@ static void setup_clocks(void) {
* present. If no bootloader is present, the user NVIC usually starts
* at the Flash base address, 0x08000000.
*/
#if defined(BOOTLOADER_maple)
#define USER_ADDR_ROM 0x08005000
#ifdef BOOTLOADER_maple
#define USER_ADDR_ROM 0x08005000
#else
#define USER_ADDR_ROM 0x08000000
#define USER_ADDR_ROM 0x08000000
#endif
#define USER_ADDR_RAM 0x20000C00
extern char __text_start__;