Merge upstream changes from Marlin 2.1.2.2
This commit is contained in:
Stefan Kalscheuer
@@ -74,17 +74,17 @@ extern "C" {
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//@{
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enum genclk_source {
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
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GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
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GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_XTAL = 6, //!< External crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_BYPASS = 7, //!< External bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_PLLACK = 8, //!< Use PLLACK as PCK source clock
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GENCLK_PCK_SRC_PLLBCK = 9, //!< Use PLLBCK as PCK source clock
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GENCLK_PCK_SRC_MCK = 10, //!< Use Master Clk as PCK source clock
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};
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//@}
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@@ -93,176 +93,162 @@ enum genclk_source {
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//@{
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enum genclk_divider {
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GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
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GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
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GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
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GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
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GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
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GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
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GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
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GENCLK_PCK_PRES_1 = PMC_PCK_PRES_CLK_1, //!< Set PCK clock prescaler to 1
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GENCLK_PCK_PRES_2 = PMC_PCK_PRES_CLK_2, //!< Set PCK clock prescaler to 2
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GENCLK_PCK_PRES_4 = PMC_PCK_PRES_CLK_4, //!< Set PCK clock prescaler to 4
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GENCLK_PCK_PRES_8 = PMC_PCK_PRES_CLK_8, //!< Set PCK clock prescaler to 8
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GENCLK_PCK_PRES_16 = PMC_PCK_PRES_CLK_16, //!< Set PCK clock prescaler to 16
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GENCLK_PCK_PRES_32 = PMC_PCK_PRES_CLK_32, //!< Set PCK clock prescaler to 32
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GENCLK_PCK_PRES_64 = PMC_PCK_PRES_CLK_64, //!< Set PCK clock prescaler to 64
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};
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//@}
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struct genclk_config {
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uint32_t ctrl;
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uint32_t ctrl;
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};
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static inline void genclk_config_defaults(struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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ul_id = ul_id;
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p_cfg->ctrl = 0;
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static inline void genclk_config_defaults(struct genclk_config *p_cfg, uint32_t ul_id) {
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ul_id = ul_id;
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p_cfg->ctrl = 0;
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}
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static inline void genclk_config_read(struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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p_cfg->ctrl = PMC->PMC_PCK[ul_id];
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static inline void genclk_config_read(struct genclk_config *p_cfg, uint32_t ul_id) {
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p_cfg->ctrl = PMC->PMC_PCK[ul_id];
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}
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static inline void genclk_config_write(const struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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static inline void genclk_config_write(const struct genclk_config *p_cfg, uint32_t ul_id) {
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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}
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//! \name Programmable Clock Source and Prescaler configuration
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//@{
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static inline void genclk_config_set_source(struct genclk_config *p_cfg,
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enum genclk_source e_src)
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{
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p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
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static inline void genclk_config_set_source(struct genclk_config *p_cfg, enum genclk_source e_src) {
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p_cfg->ctrl &= (~PMC_PCK_CSS_Msk);
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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case GENCLK_PCK_SRC_SLCK_XTAL:
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
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break;
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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case GENCLK_PCK_SRC_SLCK_XTAL:
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_SLOW_CLK);
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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p_cfg->ctrl |= (PMC_PCK_CSS_MAIN_CLK);
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break;
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case GENCLK_PCK_SRC_PLLACK:
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p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
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break;
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case GENCLK_PCK_SRC_PLLACK:
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p_cfg->ctrl |= (PMC_PCK_CSS_PLLA_CLK);
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break;
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case GENCLK_PCK_SRC_PLLBCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK);
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break;
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case GENCLK_PCK_SRC_PLLBCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_UPLL_CLK);
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break;
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case GENCLK_PCK_SRC_MCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
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break;
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}
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case GENCLK_PCK_SRC_MCK:
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p_cfg->ctrl |= (PMC_PCK_CSS_MCK);
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break;
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}
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}
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static inline void genclk_config_set_divider(struct genclk_config *p_cfg,
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uint32_t e_divider)
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{
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p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
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p_cfg->ctrl |= e_divider;
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static inline void genclk_config_set_divider(struct genclk_config *p_cfg, uint32_t e_divider) {
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p_cfg->ctrl &= ~PMC_PCK_PRES_Msk;
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p_cfg->ctrl |= e_divider;
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}
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//@}
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static inline void genclk_enable(const struct genclk_config *p_cfg,
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uint32_t ul_id)
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{
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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pmc_enable_pck(ul_id);
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static inline void genclk_enable(const struct genclk_config *p_cfg, uint32_t ul_id) {
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PMC->PMC_PCK[ul_id] = p_cfg->ctrl;
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pmc_enable_pck(ul_id);
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}
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static inline void genclk_disable(uint32_t ul_id)
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{
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pmc_disable_pck(ul_id);
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static inline void genclk_disable(uint32_t ul_id) {
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pmc_disable_pck(ul_id);
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}
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static inline void genclk_enable_source(enum genclk_source e_src)
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{
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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if (!osc_is_ready(OSC_SLCK_32K_RC)) {
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osc_enable(OSC_SLCK_32K_RC);
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osc_wait_ready(OSC_SLCK_32K_RC);
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}
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break;
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static inline void genclk_enable_source(enum genclk_source e_src) {
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switch (e_src) {
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case GENCLK_PCK_SRC_SLCK_RC:
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if (!osc_is_ready(OSC_SLCK_32K_RC)) {
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osc_enable(OSC_SLCK_32K_RC);
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osc_wait_ready(OSC_SLCK_32K_RC);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_XTAL:
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if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
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osc_enable(OSC_SLCK_32K_XTAL);
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osc_wait_ready(OSC_SLCK_32K_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_XTAL:
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if (!osc_is_ready(OSC_SLCK_32K_XTAL)) {
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osc_enable(OSC_SLCK_32K_XTAL);
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osc_wait_ready(OSC_SLCK_32K_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
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osc_enable(OSC_SLCK_32K_BYPASS);
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osc_wait_ready(OSC_SLCK_32K_BYPASS);
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}
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break;
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case GENCLK_PCK_SRC_SLCK_BYPASS:
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if (!osc_is_ready(OSC_SLCK_32K_BYPASS)) {
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osc_enable(OSC_SLCK_32K_BYPASS);
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osc_wait_ready(OSC_SLCK_32K_BYPASS);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
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osc_enable(OSC_MAINCK_4M_RC);
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osc_wait_ready(OSC_MAINCK_4M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_4M_RC:
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if (!osc_is_ready(OSC_MAINCK_4M_RC)) {
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osc_enable(OSC_MAINCK_4M_RC);
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osc_wait_ready(OSC_MAINCK_4M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
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osc_enable(OSC_MAINCK_8M_RC);
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osc_wait_ready(OSC_MAINCK_8M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_8M_RC:
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if (!osc_is_ready(OSC_MAINCK_8M_RC)) {
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osc_enable(OSC_MAINCK_8M_RC);
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osc_wait_ready(OSC_MAINCK_8M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
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osc_enable(OSC_MAINCK_12M_RC);
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osc_wait_ready(OSC_MAINCK_12M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_12M_RC:
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if (!osc_is_ready(OSC_MAINCK_12M_RC)) {
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osc_enable(OSC_MAINCK_12M_RC);
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osc_wait_ready(OSC_MAINCK_12M_RC);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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if (!osc_is_ready(OSC_MAINCK_XTAL)) {
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osc_enable(OSC_MAINCK_XTAL);
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osc_wait_ready(OSC_MAINCK_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_XTAL:
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if (!osc_is_ready(OSC_MAINCK_XTAL)) {
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osc_enable(OSC_MAINCK_XTAL);
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osc_wait_ready(OSC_MAINCK_XTAL);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
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osc_enable(OSC_MAINCK_BYPASS);
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osc_wait_ready(OSC_MAINCK_BYPASS);
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}
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break;
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case GENCLK_PCK_SRC_MAINCK_BYPASS:
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if (!osc_is_ready(OSC_MAINCK_BYPASS)) {
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osc_enable(OSC_MAINCK_BYPASS);
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osc_wait_ready(OSC_MAINCK_BYPASS);
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}
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break;
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#ifdef CONFIG_PLL0_SOURCE
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case GENCLK_PCK_SRC_PLLACK:
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pll_enable_config_defaults(0);
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break;
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#endif
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#ifdef CONFIG_PLL0_SOURCE
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case GENCLK_PCK_SRC_PLLACK:
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pll_enable_config_defaults(0);
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break;
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#endif
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#ifdef CONFIG_PLL1_SOURCE
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case GENCLK_PCK_SRC_PLLBCK:
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pll_enable_config_defaults(1);
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break;
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#endif
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#ifdef CONFIG_PLL1_SOURCE
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case GENCLK_PCK_SRC_PLLBCK:
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pll_enable_config_defaults(1);
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break;
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#endif
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case GENCLK_PCK_SRC_MCK:
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break;
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case GENCLK_PCK_SRC_MCK:
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break;
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default:
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Assert(false);
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break;
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}
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default:
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Assert(false);
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break;
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}
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}
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//! @}
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