Initial commit. Unusable Marlin 2.0.5.3 core without any custimization.
This commit is contained in:
Knutwurst
167
Marlin/src/HAL/SAMD51/timers.cpp
Executable file
167
Marlin/src/HAL/SAMD51/timers.cpp
Executable file
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/**
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* Marlin 3D Printer Firmware
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*
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* Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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* SAMD51 HAL developed by Giuliano Zaro (AKA GMagician)
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifdef __SAMD51__
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// --------------------------------------------------------------------------
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// Includes
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// --------------------------------------------------------------------------
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#include "../../inc/MarlinConfig.h"
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#include "timers.h"
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// --------------------------------------------------------------------------
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// Local defines
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// --------------------------------------------------------------------------
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#define NUM_HARDWARE_TIMERS 8
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// --------------------------------------------------------------------------
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// Private Variables
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// --------------------------------------------------------------------------
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const tTimerConfig TimerConfig[NUM_HARDWARE_TIMERS+1] = {
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{ {.pTc=TC0}, TC0_IRQn, TC_PRIORITY(0) }, // 0 - stepper
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{ {.pTc=TC1}, TC1_IRQn, TC_PRIORITY(1) }, // 1 - stepper (needed by 32 bit timers)
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{ {.pTc=TC2}, TC2_IRQn, TC_PRIORITY(2) }, // 2 - tone (framework)
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{ {.pTc=TC3}, TC3_IRQn, TC_PRIORITY(3) }, // 3 - servo
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{ {.pTc=TC4}, TC4_IRQn, TC_PRIORITY(4) }, // 4 - software serial
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{ {.pTc=TC5}, TC5_IRQn, TC_PRIORITY(5) },
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{ {.pTc=TC6}, TC6_IRQn, TC_PRIORITY(6) },
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{ {.pTc=TC7}, TC7_IRQn, TC_PRIORITY(7) },
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{ {.pRtc=RTC}, RTC_IRQn, TC_PRIORITY(8) } // 8 - temperature
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};
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// --------------------------------------------------------------------------
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// Private functions
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// --------------------------------------------------------------------------
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FORCE_INLINE void Disable_Irq(IRQn_Type irq) {
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NVIC_DisableIRQ(irq);
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// We NEED memory barriers to ensure Interrupts are actually disabled!
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// ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
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__DSB();
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__ISB();
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}
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// --------------------------------------------------------------------------
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// Public functions
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// --------------------------------------------------------------------------
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
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// Disable interrupt, just in case it was already enabled
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Disable_Irq(irq);
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if (timer_num == RTC_TIMER_NUM) {
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Rtc * const rtc = TimerConfig[timer_num].pRtc;
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// Disable timer interrupt
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rtc->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0;
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// RTC clock setup
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K; // External 32.768KHz oscillator
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// Stop timer, just in case, to be able to reconfigure it
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rtc->MODE0.CTRLA.bit.ENABLE = false;
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SYNC(rtc->MODE0.SYNCBUSY.bit.ENABLE);
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// Mode, reset counter on match
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rtc->MODE0.CTRLA.reg = RTC_MODE0_CTRLA_MODE_COUNT32 | RTC_MODE0_CTRLA_MATCHCLR;
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// Set compare value
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rtc->MODE0.COMP[0].reg = (32768 + frequency / 2) / frequency;
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SYNC(rtc->MODE0.SYNCBUSY.bit.COMP0);
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// Enable interrupt on compare
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rtc->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; // reset pending interrupt
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rtc->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; // enable compare 0 interrupt
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// And start timer
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rtc->MODE0.CTRLA.bit.ENABLE = true;
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SYNC(rtc->MODE0.SYNCBUSY.bit.ENABLE);
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}
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else {
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Tc * const tc = TimerConfig[timer_num].pTc;
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// Disable timer interrupt
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tc->COUNT32.INTENCLR.reg = TC_INTENCLR_OVF; // disable overflow interrupt
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// TCn clock setup
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const uint8_t clockID = GCLK_CLKCTRL_IDs[TCC_INST_NUM + timer_num]; // TC clock are preceeded by TCC ones
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GCLK->PCHCTRL[clockID].bit.CHEN = false;
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SYNC(GCLK->PCHCTRL[clockID].bit.CHEN);
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GCLK->PCHCTRL[clockID].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN; // 120MHz startup code programmed
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SYNC(!GCLK->PCHCTRL[clockID].bit.CHEN);
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// Stop timer, just in case, to be able to reconfigure it
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tc->COUNT32.CTRLA.bit.ENABLE = false;
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SYNC(tc->COUNT32.SYNCBUSY.bit.ENABLE);
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// Reset timer
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tc->COUNT32.CTRLA.bit.SWRST = true;
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SYNC(tc->COUNT32.SYNCBUSY.bit.SWRST);
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// Wave mode, reset counter on overflow on 0 (I use count down to prevent double buffer use)
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tc->COUNT32.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
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tc->COUNT32.CTRLA.reg = TC_CTRLA_MODE_COUNT32 | TC_CTRLA_PRESCALER_DIV1;
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tc->COUNT32.CTRLBSET.reg = TC_CTRLBCLR_DIR;
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SYNC(tc->COUNT32.SYNCBUSY.bit.CTRLB);
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// Set compare value
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tc->COUNT32.COUNT.reg = tc->COUNT32.CC[0].reg = (HAL_TIMER_RATE) / frequency;
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// Enable interrupt on compare
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tc->COUNT32.INTFLAG.reg = TC_INTFLAG_OVF; // reset pending interrupt
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tc->COUNT32.INTENSET.reg = TC_INTENSET_OVF; // enable overflow interrupt
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// And start timer
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tc->COUNT32.CTRLA.bit.ENABLE = true;
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SYNC(tc->COUNT32.SYNCBUSY.bit.ENABLE);
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}
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// Finally, enable IRQ
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NVIC_SetPriority(irq, TimerConfig[timer_num].priority);
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NVIC_EnableIRQ(irq);
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}
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void HAL_timer_enable_interrupt(const uint8_t timer_num) {
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const IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
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NVIC_EnableIRQ(irq);
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}
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void HAL_timer_disable_interrupt(const uint8_t timer_num) {
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const IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
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Disable_Irq(irq);
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}
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// missing from CMSIS: Check if interrupt is enabled or not
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static bool NVIC_GetEnabledIRQ(IRQn_Type IRQn) {
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return (NVIC->ISER[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) != 0;
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}
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bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
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const IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
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return NVIC_GetEnabledIRQ(irq);
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}
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#endif // __SAMD51__
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